Three-dimensional vertical NAND strings having one bit per cell are disclosed in an article by T. Endoh et al., titled “Novel Ultra High Density Memory With A Stacked-Surrounding Gate Transistor (S-SGT) Structured Cell,” IEDM Proc. (2001) 33-36. Drain select gate electrodes are employed to select a string of memory stack structures while deactivating other strings that share word line electrically conductive layers.